EEVEE-Next: Support for Intel ARC GPUs
This PR adds support for Intel ARC GPUs. Due barriers inside a non uniform control flow the Intel ARC can stall the whole system. The cause is that a barrier is used, but some threads in the shader have completed. The barriers might wait until it gets the signal from the exited threads and stalls the system. Although some implementations support it it is safer to limit the number of HiZ levels. Pull Request: https://projects.blender.org/blender/blender/pulls/113447
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@ -17,7 +17,7 @@
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#define LUT_WORKGROUP_SIZE 16
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/* Hierarchical Z down-sampling. */
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#define HIZ_MIP_COUNT 8
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#define HIZ_MIP_COUNT 7
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/* NOTE: The shader is written to update 5 mipmaps using LDS. */
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#define HIZ_GROUP_SIZE 32
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@ -44,7 +44,6 @@ void HiZBuffer::sync()
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hiz_update_ps_.bind_image("out_mip_4", hiz_tx_.mip_view(4));
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hiz_update_ps_.bind_image("out_mip_5", hiz_tx_.mip_view(5));
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hiz_update_ps_.bind_image("out_mip_6", hiz_tx_.mip_view(6));
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hiz_update_ps_.bind_image("out_mip_7", hiz_tx_.mip_view(7));
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/* TODO(@fclem): There might be occasions where we might not want to
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* copy mip 0 for performance reasons if there is no need for it. */
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hiz_update_ps_.push_constant("update_mip_0", true);
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@ -112,8 +112,8 @@ void main()
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mask_shift = 1;
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/* Level 7. */
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downsample_level(out_mip_7, 7);
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/* Level 7 requires barriers inside a non-uniform control flow. */
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// downsample_level(out_mip_7, 7);
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/* Limited by OpenGL maximum of 8 image slot. */
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// downsample_level(out_mip_8, 8);
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@ -121,4 +121,4 @@ void main()
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// downsample_level(out_mip_10, 10);
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}
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}
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}
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}
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@ -21,7 +21,6 @@ GPU_SHADER_CREATE_INFO(eevee_hiz_update)
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.image(4, GPU_R32F, Qualifier::WRITE, ImageType::FLOAT_2D, "out_mip_4")
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.image(5, GPU_R32F, Qualifier::READ_WRITE, ImageType::FLOAT_2D, "out_mip_5")
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.image(6, GPU_R32F, Qualifier::WRITE, ImageType::FLOAT_2D, "out_mip_6")
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.image(7, GPU_R32F, Qualifier::WRITE, ImageType::FLOAT_2D, "out_mip_7")
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.push_constant(Type::BOOL, "update_mip_0")
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.compute_source("eevee_hiz_update_comp.glsl");
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